This menu can run on a emulator under NROM header :
I want to understand what is happening in the code.
I could write this code by using NES DeCompose by BlazarSoft v.62 and FCEUX built in debugger
Please help me to write a comment for important lines :
Code: Select all
8000:78 SEI
8001:D8 CLD
8002:A2 FF LDX #$FF
8004:9A TXS
8005:A9 00 LDA #$00
8007:8D 00 20 STA $2000
800A:8D 01 20 STA $2001
800D:8D 00 E0 STA $E000
8010:A9 80 LDA #$80
8012:8D 01 A0 STA $A001
8015:A9 00 LDA #$00 ; CHR bank select command
8017:8D 00 80 STA $8000 ; Select CHR bank in the PPU
801A:A9 78 LDA #$78 ; CHR bank load command
801C:8D 01 80 STA $8001 ; Load CHR bank from ROM
801F:A9 01 LDA #$01 ; CHR bank select command
8021:8D 00 80 STA $8000 ; Select CHR bank in the PPU
8024:A9 7A LDA #$7A ; CHR bank load command
8026:8D 01 80 STA $8001 ; Load CHR bank from ROM
8029:20 AF 80 JSR $80AF
802C:20 BA 80 JSR $80BA
802F:20 D5 80 JSR $80D5
8032:20 FB 80 JSR $80FB
8035:A9 00 LDA #$00
8037:8D 00 20 STA $2000
803A:A9 00 LDA #$00
803C:8D 01 20 STA $2001
803F:8D 01 03 STA $0301
8042:A9 B3 LDA #$B3
8044:85 00 STA $0000
8046:A9 83 LDA #$83
8048:85 01 STA $0001
804A:20 1B 81 JSR $811B
804D:A9 20 LDA #$20
804F:85 04 STA $0004
8051:A9 8B LDA #$8B
8053:85 05 STA $0005
8055:20 AC 81 JSR $81AC
8058:A2 00 LDX #$00
805A:BD 12 83 LDA $8312,X @ $8312 = #$59
805D:8D 07 20 STA $2007 ; VRAM I/O Register
8060:E8 INX
8061:E0 08 CPX #$08
8063:D0 F5 BNE $805A ; $805A -09
8065:A9 21 LDA #$21
8067:85 06 STA $0006
8069:A9 04 LDA #$04
806B:85 07 STA $0007
806D:A0 00 LDY #$00
806F:20 41 81 JSR $8141
8072:20 F2 80 JSR $80F2
8075:20 33 81 JSR $8133
8078:20 F2 80 JSR $80F2
807B:A9 00 LDA #$00
807D:8D 05 03 STA $0305
8080:A9 00 LDA #$00
8082:8D 00 20 STA $2000 ; PPU1
8085:A9 18 LDA #$18
8087:8D 01 20 STA $2001 ; PPU2
808A:A9 FF LDA #$FF
808C:8D 15 40 STA $4015 ; Sound/Vertical Clock Signal Register
808F:A9 00 LDA #$00
8091:8D 03 20 STA $2003 ; SPR-RAM Address Register
8094:A9 02 LDA #$02
8096:8D 14 40 STA $4014 ; Sprite DMA Register
8099:A2 00 LDX #$00
809B:20 AF 80 JSR $80AF
809E:E8 INX
809F:E0 0A CPX #$0A
80A1:D0 F8 BNE $809B ; $809B -06
80A3:20 FC 81 JSR $81FC
80A6:20 13 82 JSR $8213
80A9:20 F2 80 JSR $80F2
80AC:4C 8F 80 JMP $808F
80AF:AD 02 20 LDA $2002 ; PPU Status
80B2:30 FB BMI $80AF ; $80AF -03
80B4:AD 02 20 LDA $2002 ; PPU Status
80B7:10 FB BPL $80B4 ; $80B4 -03
80B9:60 RTS
80BA:A2 00 LDX #$00
80BC:8A TXA
80BD:95 00 STA $00,X @ $00FF
80BF:9D 00 02 STA $0200,X @ $02FF
80C2:9D 00 03 STA $0300,X @ $03FF
80C5:9D 00 04 STA $0400,X @ $04FF
80C8:9D 00 05 STA $0500,X @ $05FF
80CB:9D 00 06 STA $0600,X @ $06FF
80CE:9D 00 07 STA $0700,X @ $07FF
80D1:CA DEX
80D2:D0 E9 BNE $80BD ; $80BD -15
80D4:60 RTS
80D5:A9 00 LDA #$00
80D7:18 CLC
80D8:69 20 ADC #$20
80DA:8D 06 20 STA $2006 ; VRAM Address Register #2
80DD:A9 00 LDA #$00
80DF:8D 06 20 STA $2006 ; VRAM Address Register #2
80E2:A9 5F LDA #$5F
80E4:A2 04 LDX #$04
80E6:A0 00 LDY #$00
80E8:8D 07 20 STA $2007 ; VRAM I/O Register
80EB:C8 INY
80EC:D0 FA BNE $80E8 ; $80E8 -04
80EE:CA DEX
80EF:D0 F5 BNE $80E6 ; $80E6 -09
80F1:60 RTS
80F2:A9 00 LDA #$00
80F4:8D 05 20 STA $2005 ; VRAM Address Register #1
80F7:8D 05 20 STA $2005 ; VRAM Address Register #1
80FA:60 RTS
80FB:A9 23 LDA #$23
80FD:8D 06 20 STA $2006 ; VRAM Address Register #2
8100:A9 C0 LDA #$C0
8102:8D 06 20 STA $2006 ; VRAM Address Register #2
8105:A9 00 LDA #$00
8107:A2 10 LDX #$10
8109:20 14 81 JSR $8114
810C:A9 FF LDA #$FF
810E:A2 30 LDX #$30
8110:20 14 81 JSR $8114
8113:60 RTS
8114:8D 07 20 STA $2007 ; VRAM I/O Register
8117:CA DEX
8118:D0 FA BNE $8114 ; $8114 -04
811A:60 RTS
811B:A0 3F LDY #$3F
811D:A9 00 LDA #$00
811F:8C 06 20 STY $2006 ; VRAM Address Register #2
8122:8D 06 20 STA $2006 ; VRAM Address Register #2
8125:A0 00 LDY #$00
8127:A2 20 LDX #$20
8129:B1 00 LDA ($00),Y @ $83B3 = #$01
812B:8D 07 20 STA $2007 ; VRAM I/O Register
812E:C8 INY
812F:CA DEX
8130:D0 F7 BNE $8129 ; $8129 -07
8132:60 RTS
8133:A2 00 LDX #$00
8135:BD D3 83 LDA $83D3,X @ $83D3 = #$40
8138:9D 00 02 STA $0200,X @ $0200
813B:E8 INX
813C:E0 10 CPX #$10
813E:D0 F5 BNE $8135 ; $8135 -09
8140:60 RTS
8141:A9 1A LDA #$1A
8143:85 08 STA $0008
8145:A9 83 LDA #$83
8147:85 09 STA $0009
8149:A5 06 LDA $0006 = #$21
814B:85 04 STA $0004
814D:A5 07 LDA $0007 = #$04
814F:85 05 STA $0005
8151:20 AF 80 JSR $80AF
8154:20 AC 81 JSR $81AC
8157:B1 08 LDA ($08),Y @ $831A = #$00
8159:AA TAX
815A:E0 FE CPX #$FE
815C:F0 1A BEQ $8178 ; $8178 +1C (Return)
815E:E0 FF CPX #$FF
8160:F0 17 BEQ $8179 ; $8179 +19
8162:8E 07 20 STX $2007 ; VRAM I/O Register
8165:E8 INX
8166:8E 07 20 STX $2007 ; VRAM I/O Register
8169:20 8D 81 JSR $818D
816C:E8 INX
816D:8E 07 20 STX $2007 ; VRAM I/O Register
8170:E8 INX
8171:8E 07 20 STX $2007 ; VRAM I/O Register
8174:C8 INY
8175:4C 54 81 JMP $8154
8178:60 RTS
8179:20 B7 81 JSR $81B7
817C:A9 40 LDA #$40
817E:18 CLC
817F:65 07 ADC $0007 = #$04
8181:85 07 STA $0007
8183:A9 00 LDA #$00
8185:65 06 ADC $0006 = #$21
8187:85 06 STA $0006
8189:C8 INY
818A:4C 41 81 JMP $8141
818D:A9 20 LDA #$20
818F:18 CLC
8190:65 05 ADC $0005 = #$04
8192:48 PHA
8193:A9 00 LDA #$00
8195:65 04 ADC $0004 = #$21
8197:8D 06 20 STA $2006 ; VRAM Address Register #2
819A:68 PLA
819B:8D 06 20 STA $2006 ; VRAM Address Register #2
819E:A9 02 LDA #$02
81A0:18 CLC
81A1:65 05 ADC $0005 = #$04
81A3:85 05 STA $0005
81A5:A9 00 LDA #$00
81A7:65 04 ADC $0004 = #$21
81A9:85 04 STA $0004
81AB:60 RTS
81AC:A5 04 LDA $0004 = #$20
81AE:8D 06 20 STA $2006 ; VRAM Address Register #2
81B1:A5 05 LDA $0005 = #$8B
81B3:8D 06 20 STA $2006 ; VRAM Address Register #2
81B6:60 RTS
81B7:20 8D 81 JSR $818D
81BA:A9 FF LDA #$FF
81BC:8D 07 20 STA $2007 ; VRAM I/O Register
81BF:C8 INY
81C0:B1 08 LDA ($08),Y @ $831E = #$FF
81C2:AA TAX
81C3:E0 FD CPX #$FD
81C5:F0 07 BEQ $81CE ; $81CE +09 (Return)
81C7:8E 07 20 STX $2007 ; VRAM I/O Register
81CA:C8 INY
81CB:4C C0 81 JMP $81C0
81CE:60 RTS
81CF:40 RTI
81D0:AD 05 03 LDA $0305 = #$00
81D3:AA TAX
81D4:BD E3 83 LDA $83E3,X @ $84E0 = #$00
81D7:8D 00 02 STA $0200
81DA:8D 08 02 STA $0208
81DD:18 CLC
81DE:69 08 ADC #$08
81E0:8D 04 02 STA $0204
81E3:8D 0C 02 STA $020C
81E6:60 RTS
81E7:A9 1F LDA #$1F
81E9:8D 04 40 STA $4004 ; pAPU Pulse #2 Ctrl Register
81EC:A9 99 LDA #$99
81EE:8D 05 40 STA $4005 ; pAPU Pulse #2 Ramp Ctrl Register
81F1:A9 EF LDA #$EF
81F3:8D 06 40 STA $4006 ; pAPU Pulse #2 Fine Tune Register
81F6:A9 08 LDA #$08
81F8:8D 07 40 STA $4007 ; pAPU Pulse #2 Coarse Tune Register
81FB:60 RTS
81FC:A2 01 LDX #$01
81FE:8E 16 40 STX $4016 ; Gamepad #1
8201:A2 00 LDX #$00
8203:8E 16 40 STX $4016 ; Gamepad #1
8206:A0 08 LDY #$08
8208:AD 16 40 LDA $4016 = #$FF ; Gamepad #1
820B:4A LSR
820C:2E 04 03 ROL $0304 = #$00
820F:88 DEY
8210:D0 F6 BNE $8208 ; $8208 -08
8212:60 RTS
8213:A9 08 LDA #$08
8215:CD 04 03 CMP $0304 = #$00
8218:F0 16 BEQ $8230 ; $8230 +18
821A:A9 04 LDA #$04
821C:CD 04 03 CMP $0304 = #$00
821F:F0 26 BEQ $8247 ; $8247 +28
8221:A9 10 LDA #$10
8223:CD 04 03 CMP $0304 = #$00
8226:F0 36 BEQ $825E ; $825E +38
8228:A9 C0 LDA #$C0
822A:2C 04 03 BIT $0304 = #$00
822D:D0 2F BNE $825E ; $825E +31
822F:60 RTS
8230:20 E7 81 JSR $81E7 ; related to up button
8233:AD 05 03 LDA $0305 = #$07
8236:F0 07 BEQ $823F ; $823F +09
8238:CE 05 03 DEC $0305 = #$07
823B:20 D0 81 JSR $81D0
823E:60 RTS
823F:A9 07 LDA #$07 ; Limit games selection toward up
8241:8D 05 03 STA $0305
8244:4C 3B 82 JMP $823B
8247:20 E7 81 JSR $81E7
824A:AD 05 03 LDA $0305 = #$00
824D:C9 07 CMP #$07 ; Limit games selection toward down
824F:F0 06 BEQ $8257 ; $8257 +08
8251:EE 05 03 INC $0305 = #$00
8254:4C 3B 82 JMP $823B
8257:A9 00 LDA #$00
8259:8D 05 03 STA $0305
825C:F0 DD BEQ $823B ; $823B -21
825E:A9 00 LDA #$00
8260:8D 00 20 STA $2000 ; PPU1
8263:8D 01 20 STA $2001 ; PPU2
8266:8D 15 40 STA $4015 ; Sound/Vertical Clock Signal Register
8269:AD 05 03 LDA $0305 = #$00
826C:C9 05 CMP #$05 ; Set default slot for running initial game
826E:D0 13 BNE $8283 ; $8283 +15
8270:20 BA 80 JSR $80BA
8273:A9 80 LDA #$80
8275:8D 01 A0 STA $A001
8278:A9 C9 LDA #$C9
827A:8D 00 68 STA $6800
827D:4C 8D F9 JMP $F98D ; *JUMP TO START OF THE GAME*
8280:4C 00 C0 JMP $C000
8283:20 89 82 JSR $8289
8286:4C 00 04 JMP $0400
8289:A2 00 LDX #$00
828B:BD 97 82 LDA $8297,X @ $8297 = #$AD
828E:9D 00 04 STA $0400,X @ $0400
8291:E8 INX
8292:E0 80 CPX #$80
8294:D0 F5 BNE $828B ; $828B -09
8296:60 RTS
8297 : AD 05 03 C9 00 F0 1C C9 01
82A0 : F0 20 C9 02 F0 24 C9 03 F0 28 C9 04 F0 2C C9 06
82B0 : F0 30 A9 FB 8D 00 68 4C 53 04 A9 CC 8D 00 68 4C
82C0 : 53 04 A9 DD 8D 00 68 4C 53 04 A9 EE 8D 00 68 4C
82D0 : 53 04 A9 FF 8D 00 68 4C 53 04 A9 D8 8D 00 68 4C
82E0 : 53 04 A9 EA 8D 00 68 4C 53 04 A9 80 8D 01 A0 A0
82F0 : 00 A2 00 A9 00 95 00 9D 00 01 9D 00 02 9D 00 03
8300 : 9D 00 06 9D 00 05 9D 00 07 CA D0 E9 8D 00 E0 6C
8310 : FC FF 59 5F 5F 5A 5B 5F 5F 58 00 04 08 0C FF 91
8320 : 8E 9B 98 8E 9C AF 8F 92 90 91 9D 92 97 90 FD 00
8330 : 04 10 14 FF 8D 98 8D 90 8E AF 8B 8A 95 95 FD 00
8340 : 04 18 1C FF 91 8E 9B 98 8E 9C AF 9C 9D 98 9B A2
8350 : FD 00 04 68 6C 70 FF 9C 99 98 9B 9D 9C AF 96 8E
8360 : 8E 9D 92 97 90 FD 00 04 28 24 FF 91 8E 9B 98 8E
8370 : 9C AF 92 8C 8E AF 91 98 8C 94 8E A2 FD 00 04 2C
8380 : 24 FF 9F 98 95 95 8E A2 AF 8B 8A 95 95 FD 00 04
8390 : 20 24 FF 91 8E 9B 98 8E 9C AF 90 98 8A 95 AF 83
83A0 : FD 00 04 30 24 FF 8B 8A 9C 94 8E 9D AF 8B 8A 95
83B0 : 95 FD FE 01 96 96 96 0F F0 F0 F6 0F F0 F0 F0 0F
83C0 : F6 36 36 01 26 26 35 0F 26 27 F9 0F 15 21 30 0F
83D0 : 15 29 30 40 54 00 10 48 56 00 10 40 55 00 18 48
83E0 : 57 00 18 40 50 60 70 80 90 A0 B0
FF80:78 SEI
FF81:D8 CLD
FF82:A9 00 LDA #$00
FF84:8D 00 20 STA $2000 ; PPU1 ;Base nametable address
FF87:8D 01 20 STA $2001 ; PPU2
FF8A:A2 04 LDX #$04
FF8C:AC 02 20 LDY $2002 = #$00 ; PPU Status
FF8F:10 FB BPL $FF8C ; $FF8C -03 ;Jump until S or 7 bit of LD? will be set
FF91:AC 02 20 LDY $2002 = #$00 ; PPU Status
FF94:30 FB BMI $FF91 ; $FF91 -03
FF96:CA DEX
FF97:10 F3 BPL $FF8C ; $FF8C -0B
FF99:9A TXS
FF9A:8D 00 20 STA $2000 ; PPU1
FF9D:8D 01 20 STA $2001 ; PPU2
FFA0:A9 00 LDA #$00
FFA2:8D 00 80 STA $8000
FFA5:8D 00 A0 STA $A000
FFA8:A9 80 LDA #$80
FFAA:8D 01 A0 STA $A001
FFAD:8D 00 E0 STA $E000
FFB0:A9 06 LDA #$06 ; PRG bank select command
FFB2:8D 00 80 STA $8000 ; Select PRG bank in the CPU
FFB5:A9 17 LDA #$17 ; PRG bank load command
FFB7:8D 01 80 STA $8001 ; Load PRG bank from ROM
FFBA:4C 00 80 JMP $8000
FFE6:A9 90 LDA #$90
FFE8:8D 01 A0 STA $A001
FFEB:8D 00 70 STA $7000
FFEE:D0 90 BNE $FF80 ; $FF80 -6E
FFF0:A9 80 LDA #$80
FFF2:8D 01 A0 STA $A001 ; Enable SRAM
FFF5:EA NOP
FFF6:EA NOP
FFF7:EA NOP
FFF8:D0 86 BNE $FF80 ; $FF80 -78 ;Check Zero Flag if is clear
FFFA: .db $3F ; NMI / VBLANK vector: $FF3F
FFFB: .db $FF
FFFC: .db $F0 ; Reset vector: $FFF0
FFFD: .db $FF
FFFE: .db $42 ; IRQ / BRK vector: $FF42
FFFF: .db $FF