7F48h ... This register is "secondary ROM enable".
That's an unexpected feature. Aside from the anti-dumping effect, it might be intended to R/W-protect SRAM (when using ROM+SRAM instead 2xROM), or to switch addressing for boards with 1 or 2 ROMs.
Are you sure it's controlled by 7F48h? The way how 7F48h is used in software looks entirely different than what you described. For example, in the ROM checksum calculation (at 13FAE0h in Megaman X2), 7F48h is toggled after checksumming every 800h byte block. And, after writing 7F48h, the software seems to wait for a busy-flag.
My conclusion was that it loads the cache (source in program counter register, and destination 0 or 1 in 7F48h (in case of checksumming stuff that wouldn't make too much sense though)). Whereas... cache-loading may in fact temporarily "disable" the ROMs.
Code: Select all
612Eh movb ext_dta,[ext_ptr] ;\these 3 opcodes are used to
4000h inc ext_ptr ; read one byte from [ext_ptr],
1C00h finish ext_dta ;/and to increment ext_ptr by 1
I can only guess there, too. Doing (or invoking) the memory access in 1st opcode makes most sense to me. Yup, the 3rd opcode may be a "wait", or just forwarding the result in case the memory access can be finished within the 3 opcodes without waiting. And the 2nd opcode, maybe it's doing some memory-access stuff, too, the only thing that is sure is that it does increment ext_ptr (inconsistent with the architecture or not).
What I really want is to find someone who can replace the second ROM chip on Rockman X2 with a RAM chip.
Would be nice. And not very complicated: Basically a 32pin SRAM mounted with 1:1 connection on top of the 32pin ROM, plus a switch to select between ROM and SRAM, and finding a /WR write signal from the CX4 chip (or if the thing doesn't have a /WR signal, then it'd be easiest to use a EPROM or FLASH chip instead of SRAM).
if you ever get bored and want to take a look, Cydrak and I found what appears to be a timer in the ST018
When I've time. At the moment I've focused on bugfixes, and SFC-Box...
Super Famicom Box:
Here's a new KROM1 replacement with diagnostics functions:
http://nocash.emubase.de/kromtest.zip Would be great if somebody could burn it into EPROM (27C512), and then replace the KROM1 by that chip.
It's showing the full OSD character set, different character sizes, mono and color palettes, background "bordering" styles, etc. Plus I/O port dumps, some CPU invalid-opcode TRAP tests, button/switch test, and some "pulse" and "toggle" functions for unknown outputs (some that might blink the LEDs... or possibly produce BEEP sounds in case there's an external audio source).
Best would be taking JPG screenshots of all test screens with some video grabbing hardware (should be better quality than photos). Though picture quality doesn't matter too much for now, at the moment I'd be just happy to see if/how it's working on real hardware.
So far, I've tested it only in no$sns (where it's working fine). Real hardware seems to include a watchdog, but that should be handled, so I hope the program won't crash or hang!
Oh, and some general questions: That GAME/TV button... does that have any visible effect on video input or output? Or maybe pauses the game while in TV mode? Ah, and is it a "normal" push-button, closed when/while pushed, or is it closed when pushed once, and opened when pushed another time? And same for the RESET button?
The right-most switch setting... is it possible that the relay does switch-off the SFC-Box (rather than switching-off the TV-Set)?
Some (maybe only newer) MBxxxxx OSD chips seem to have a Blink-feature, is there such a thing used in the SFC-Box, too? (If yes, it might appear in the "OSD STYLES" test).
And are there any "external" non-APU sound effects? The menu is using the APU, but maybe there are in-game sounds, prompting for new-coin, or confirming coin-insertion. (If there's such a feature, then it's probably merely a BEEP sound, and sould be heard in the "PULSE" tests).