CPY, BPL, and absolute indexed addressing questions

[noattack]

A quick elementary assembly question I'm puzzling over:

Code: Select all

LDY #$04
CPY #$04
BPL label

When the compare results are equal, does the N-flag remain 0 and thus the branch is taken?

Now, a similar question with a two's complement twist:

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LDY #$84
CPY #$04
BPL label

Am I correct that the result of the CPY ($80) is -128 in two's complement and the branch will be skipped?

Finally, a slightly related question on absolute indexed addressing:

Code: Select all

LDY #$80
LDA DATA, Y

Is Y treated as a positive or negative index? In other words, does indexing ignore two's complement?

[lidnariq]

A quick elementary assembly question I'm puzzling over:

Code: Select all

LDY #$04
CPY #$04
BPL label

When the compare results are equal, does the N-flag remain 0 and thus the branch is taken?

4 - 4 = 0; bit seven remains clear so N is 0, BPL takes the branch

Now, a similar question with a two's complement twist:

Code: Select all

LDY #$84
CPY #$04
BPL label

Am I correct that the result of the CPY ($80) is -128 in two's complement and the branch will be skipped?

The CPU doesn't really do signed math for you.

0x84 = 132; 132-4 = 128; bit seven is set so N is set so the BPL doesn't follow.

Finally, a slightly related question on absolute indexed addressing:

Code: Select all

LDY #$80
LDA DATA, Y

Is Y treated as a positive or negative index? In other words, does indexing ignore two's complement?

Indices are unsigned. It's not so much that it just "ignores" two's complement here (although it does), it's that on the 6502 it barely supports signed math at all. (relative addresses for branches and the N bit are it)

[noattack]

Thanks for the answers. I guess I was over-thinking the CPU's 'perception' of negative values. It has no sense of positive or negative - it just does or does not set the flag.

[tepples]

The only places I can think of where the 6502 treats a value with its high bit set as a negative number are A. branch offsets, and B. setting the V flag in an ADC or SBC. Otherwise, the sign flag (bit 7 of P) just refers to bit 7 of the previous result.