nesdev.org

google provides this link from the image in the patent: http://patentimages.storage.googleapis. ... 0655-1.png

The patent looks like it expired in 2003 due to failure to pay maintenance fees. It should have expired in 2007 regardless.

The 74HC74 datasheet indicates two separate inverters in its truth table: The claims look to narrow enough that with that we should be able (were it necessary) to make a "technically doesn't do what the patent specifies" by using the other inverter inside the first flipflop.
- Tie Z1A CP and D high
- Tie Z1A /R low
- Move the crystal-resistor-capacitor blob to between Z1A /S and Z1A Q
- Tie Z1B CP to Z1A Q instead.

If I had a 74HC74 lying around I'd try both, to double-check and make sure it worked at higher frequency crystals.

lidnariq wrote:google provides this link from the image in the patent: http://patentimages.storage.googleapis. ... 0655-1.png

The patent looks like it expired in 2003 due to failure to pay maintenance fees. It should have expired in 2007 regardless.

The 74HC74 datasheet indicates two separate inverters in its truth table:

Code: Select all

Input    Output	
/SD /RD  Q /Q
 L   H   H  L
 H   L   L  H
 L   L   H  H

The claims look to narrow enough that with that we should be able (were it necessary) to make a "technically doesn't do what the patent specifies" by using the other inverter inside the first flipflop.
- Tie Z1A CP and D high
- Tie Z1A /R low
- Move the crystal-resistor-capacitor blob to between Z1A /S and Z1A Q
- Tie Z1B CP to Z1A Q instead.

If I had a 74HC74 lying around I'd try both, to double-check and make sure it worked at higher frequency crystals.

Thanks, Very cool. Will knock it together in abit. Will have to use what ever xtal val I have on hand to test, sure I have a 16MHz ( AVR/Arduino stuff). Same ball park
Any thoughts on the feedback R, I'm guessing something around 1M?
Yogi

1M is as good of a guess as any. The 74HC74 as used here is equivalent to three CMOS inverters in series, whatever impact that'll have...

lidnariq wrote:

YM3812: readily available oscillator, needs external DAC YM3014 or similar (costs more than synth), no mixing needed.

Hm. The complexity of translating the bitstream to ordinary I²S is definitely within the range of the least CPLD, if not just a microcontroller. And the cheapest I²S DAC I can find is also about a dollar.

I²S? or I²C? Granted I didn't look too hard, but digikey turned up a I²S DAC for $1.50, and I²C for ~$0.60. IDK the thought of utlizing a CPLD/mcu for DAC feels like overkill. I know it's really not when you just look at price, but when you consider you could put a synth in the mcu instead it just feels wrong to use a mcu just for that.

The benefits I see of using the yamaha line including the DAC is it's more turn key development. That and it's standardized to some degree. The components aren't new, but they're reasonably sourced. Additionally I can always leave the sourcing/choice of the specific OPL and DAC to the user to assemble themselves. In reality I don't think and of this is going to end up in volume production anyways. The real motivation for this right now is just to get a FM synth in the hands of guys like yogi without hacking up a famicom cart.

Then again, new old stock or working pulls of the YMF262 (OPL3) are also about the same cost as the YM3812 on ebay, and its DAC looks to be usually cheaper than the OPL3.

This combo does seem like a better solution compared to the OPL2 and YM3014 depending on goals. Making a shield for them to be soldered onto as one unit would be a neat way to keep em socketed too. I could make the shield pin compatible with the ay-3-8910 which is already wired up, probably throw an opamp and discretes on there all together too.

infiniteneslives wrote:

lidnariq wrote:

YM3812: readily available oscillator, needs external DAC YM3014 or similar (costs more than synth), no mixing needed.

Hm. The complexity of translating the bitstream to ordinary I²S is definitely within the range of the least CPLD, if not just a microcontroller. And the cheapest I²S DAC I can find is also about a dollar.

I²S? or I²C? Granted I didn't look too hard, but digikey turned up a I²S DAC for $1.50, and I²C for ~$0.60. IDK the thought of utlizing a CPLD/mcu for DAC feels like overkill. I know it's really not when you just look at price, but when you consider you could put a synth in the mcu instead it just feels wrong to use a mcu just for that.
The benefits I see of using the yamaha line including the DAC is it's more turn key development. That and it's standardized to some degree. The components aren't new, but they're reasonably sourced. Additionally I can always leave the sourcing/choice of the specific OPL and DAC to the user to assemble themselves. In reality I don't think and of this is going to end up in volume production anyways. The real motivation for this right now is just to get a FM synth in the hands of guys like yogi without hacking up a famicom cart.

For the scope of what we're discussing, the added cost of an 'all Yamaha' solution seems worth it for a simpler design. The R&D to adapt a modern DAC does not seem trivial and I'm afraid it would really add to feature creep. Not that it's unobtainable, it just looks like a minefield of unknown issues to overcome when there is already a growing todo list

Then again, new old stock or working pulls of the YMF262 (OPL3) are also about the same cost as the YM3812 on ebay, and its DAC looks to be usually cheaper than the OPL3.

This combo does seem like a better solution compared to the OPL2 and YM3014 depending on goals. Making a shield for them to be soldered onto as one unit would be a neat way to keep em socketed too. I could make the shield pin compatible with the ay-3-8910 which is already wired up, probably throw an opamp and discretes on there all together too.

Very interesting idea, I like it. If the OPL3 is an option on the table, for prototyping I might recommend the MBFM board. It's available through SmashTV's shop at $8. http://www.midibox-shop.com/buy.html
It's far too large to be viable within an NES cart but for proof of concept and dev it could help?
If you do develop a OPL3 shield, going all SMT would shrink it quite a bit even though that would complicate DIY building. I've had good results hand soldering down to 0805 parts if the layout isn't too tight, so I would be up for a bare board. But I'm sure many would need/like a prebuilt option. Which of course leads back to the demand of an inventory of parts and sourcing issues.
Just gotta say the interest and support in this effort is really great from everyone! Even the OPLL expansion would be of major interest to a number of chiptune musicians; an OPL2/3 or OPN2 board might cause riots in the streets!
Yogi

lidnariq wrote:google provides this link from the image in the patent: http://patentimages.storage.googleapis. ... 0655-1.png

The patent looks like it expired in 2003 due to failure to pay maintenance fees. It should have expired in 2007 regardless.

Well good news and bad news.
First: I'm using HCT74s, R=1M, C=22pF
The first tests I've run are on solderless proto boards so there is a lot of stray C, but with a 2MHz xtal the Osc side does start up fine. The only way I can couple to the /2 FF is by running the /Q output through a HCT14 inverter gate. Also, with the osc running I can see the 2MHz signal at the /Q - Xtal node but not at the Q output; I thought that this should be oscillating also, due to the /Q-Reset oscillations, strange.
If I directly couple the output to the CP input of the /2 stage, as per the patent doc, I see the 2MHz signal at it's outputs with no division. Inputting a higher drive level signal (my 3.58MHz HCT14 osc) to the divider works fine.
Moving on to a 8MHz and then a 16MHz xtal worked as per above (had to set up a second HCT 74 as a /4 prescaler; my DMM F counter tops out at 4MHz.) So it seems to work in this 2chip solution but would be nice to have only 1 chip.
So I will be trying to adjust the feedback R values to get better drive out of the osc and eliminate the HCT 14 gate.
Yogi
EDIT
YEA! After doing a better search and reading the Patent, I got a little better understanding of the operation.

The resistance of R1 and the capacitance of C1 are selected such that the time constant R1C1 is much longer than the time for one half cycle of the crystal's resonant frequency.

This is somewhat flexible from my tests , the patent circuit ran with a verity of 14 through 16 MHz xtals; using the combo of C=370pF and R=10M. A NOT gate was not needed!

yogi wrote:The only way I can couple to the /2 FF is by running the /Q output through a HCT14 inverter gate.
[…]
If I directly couple the output to the CP input of the /2 stage, as per the patent doc, I see the 2MHz signal at its outputs with no division. Inputting a higher drive level signal (my 3.58MHz HCT14 osc) to the divider works fine.

Hm. What kind of voltage swing are you seeing on /Q?
The only guess I have is maybe HCT voltage thresholds are inappropriate for cascading here, so this might only work with 74HC or 74AC gates. The datasheet seems to indicate a schmidt trigger input on the clock lines, though, so I'm not clear why the separate schmidt trigger inverter would work while the integrated one wouldn't.

I was going to initially suspect loading, and suggest replacing the '14 buffer with a large resistor ... but that would have stopped the oscillator, not the ÷2.
You might also be able to use a large resistor divider to move the center voltage of oscillation ... but that won't help if the amplitude is too low.

Also, with the osc running I can see the 2MHz signal at the /Q - Xtal node but not at the Q output; I thought that this should be oscillating also, due to the /Q-Reset oscillations, strange.

Unfortunately when using the half of the 7474 as an oscillator we don't get SR latch behavior anymore: Q (per the truth table above) will remain high.

So it seems to work in this 2chip solution but would be nice to have only 1 chip.

Bad comes to worse, we could use a 74'1G14. (It's as cheap as a single MOSFET anyway)

lidnariq wrote:

yogi wrote:The only way I can couple to the /2 FF is by running the /Q output through a HCT14 inverter gate.
[…]
If I directly couple the output to the CP input of the /2 stage, as per the patent doc, I see the 2MHz signal at its outputs with no division. Inputting a higher drive level signal (my 3.58MHz HCT14 osc) to the divider works fine.

Hm. What kind of voltage swing are you seeing on /Q?
The only guess I have is maybe HCT voltage thresholds are inappropriate for cascading here, so this might only work with 74HC or 74AC gates. The datasheet seems to indicate a schmidt trigger input on the clock lines, though, so I'm not clear why the separate schmidt trigger inverter would work while the integrated one wouldn't.

I was going to initially suspect loading, and suggest replacing the '14 buffer with a large resistor ... but that would have stopped the oscillator, not the ÷2.
You might also be able to use a large resistor divider to move the center voltage of oscillation ... but that won't help if the amplitude is too low.

Also, with the osc running I can see the 2MHz signal at the /Q - Xtal node but not at the Q output; I thought that this should be oscillating also, due to the /Q-Reset oscillations, strange.

Unfortunately when using the half of the 7474 as an oscillator we don't get SR latch behavior anymore: Q (per the truth table above) will remain high.

So it seems to work in this 2chip solution but would be nice to have only 1 chip.

Bad comes to worse, we could use a 74'1G14. (It's as cheap as a single MOSFET anyway)

(I ninja-ed your post editing my last post above.)
Turned out it was a matter of the free running RC OSC needing to be lower; Increased my R to 10M and C to 370pF got the Xtal circuit running in the 16 MHz range My values aren't optimized; just happy it's running.
On a side note, I located the Yamaha datasheet for the YM2608 (the parent of the YM2612; the same FM core). the Interesting thing I found is it's nom Master CLK is 8MHz, so I think Sega just under-clocked it, based on the chosen system clock. So, could use a standard 8 MHz can; but it may be better to maintain compatibility with Sega VGM values?
Yogi

yogi wrote:Turned out it was a matter of the free running RC OSC needing to be lower; Increased my R to 10M and C to 370pF got the Xtal circuit running in the 16 MHz range My values aren't optimized; just happy it's running.

Weird. The original frequency was already just 7kHz, I'm surprised dropping it to 40Hz helped things (as opposed to, say, simply reducing the strength of the bias resistor). Or maybe the extra capacitive load did something. That large of a capacitance should definitely drop the effective frequency of the crystal, though. (How do 22pF and 370pF compare to the parallel parasitic capacitance of the crystal?)

yogi wrote:On a side note, I located the Yamaha datasheet for the YM2608 (the parent of the YM2612; the same FM core). the Interesting thing I found is it's nominal Master CLK is 8MHz, so I think Sega just under-clocked it, based on the chosen system clock. So, could use a standard 8 MHz can; but it may be better to maintain compatibility with Sega VGM values?

Hm. I wonder. Page 19 of the translated OPNA datasheet shows there's a selectable clock divider of 2,3, or 6 for the FM synth, but I'm not certain what else that changes. After all, the OPNA contains its own DAC, so there's no minimum clock speed to hold a serial bitstream. Anyway, when at a divider of 6 (claimed necessary for behavior above 4MHz), the output sample clock is Mclk/144. (Much like the OPL3's is Mclk/288, or the OPL2's is Mclk/72).

Beyonds changing the necessary tuning tables, this will also slightly affect ADSR rates, the timers, and the various free-running LFOs (e.g. "AMS" and "PMS"). Not certain exactly what they're using, since their rates don't seem to be tunable.

If we can extrapolate from the OPL3, the FM LFO is fixed at Sclk÷8192, and the AM LFO is fixed at Sclk÷13440. (MESS says these magic numbers are shared with the rest of the OPLx family, but who knows if that's true for the OPNx. Apparently the OPMx family can actually control the LFOs!)
----------------------

infiniteneslives wrote:I²S? or I²C? Granted I didn't look too hard, but digikey turned up a I²S DAC for $1.50, and I²C for ~$0.60.

I²S. I²C can't maintain the necessary bandwidth (at least 2+3×9=29 bittimes per sample, so 1.4Mbit/s). But let's drop this, for the other reasons you laid out.

lidnariq wrote:Then again, new old stock or working pulls of the YMF262 (OPL3) are also about the same cost as the YM3812 on ebay, and its DAC [YAC512] looks to be usually cheaper than the OPL3.

Gluing these two trains of though together, I thought I'd go ahead and compare the bitstreams we're talking about here:

YM3014 (OPL2 DAC) input format
- 16 clocks per sample (800kHz)
- monaural
- falling edge of word clock marks end of word
- three idle bit periods per word (650kbit/s)
- UNsigned, LITTLE endian, µ-law-like

YMF262 (OPL3) output format
- 18 clocks per sample (1.79MHz)
- two channels interleaved per data line, two data lines, nominally quadraphonic
- two word clock lines, falling edge marks end of word
- two idle bit periods per word (3.2Mbit/s)
- UNsigned, LITTLE endian, PCM

I²S stream
- any number of clocks per sample, but many receivers require at least 8
- two channels interleaved per data line
- word clock toggles on bit before end of word
- Signed, BIG endian
- Many DACs annoyingly require a clock input at 256 times the sample rate.


And one even bigger tangent: Since the OPL3 doesn't really support "useful" quadraphonics (each voice can either be mixed or skipped for each output channel), I thought it would be nifty to have controllable VCFs on the DACs' outputs, and downmix that all to mono. But a digitally controlled VCF should really be done all in DSP anyway, so that's really just a pipedream.

lidnariq wrote:- Many DACs annoyingly require a clock input at 256 times the sample rate.

I wonder whether that has anything to do with using a narrower (or even 1-bit) DAC and dithering to push the quantization noise into ultrasound. This is, for example, why SACD uses a sample rate of 64*CD.

tepples wrote:

lidnariq wrote:- Many DACs annoyingly require a clock input at 256 times the sample rate.

I wonder whether that has anything to do with using a narrower (or even 1-bit) DAC and dithering to push the quantization noise into ultrasound. This is, for example, why SACD uses a sample rate of 64*CD.

Probably, these are almost certainly sigma-delta DAC.

Weird. The original frequency was already just 7kHz, I'm surprised dropping it to 40Hz helped things (as opposed to, say, simply reducing the strength of the bias resistor). Or maybe the extra capacitive load did something. That large of a capacitance should definitely drop the effective frequency of the crystal, though. (How do 22pF and 370pF compare to the parallel parasitic capacitance of the crystal?)

My observation with the original RC osc (no Xtal in circuit) measured @ ~16MHz. In the early stages of my poking, I had tried a 10M with the 22pf value but it had the same problems as stated earlier. After reading the Pat.; just increasing C to ~30pF started it running without the HCT14 gate.
I then began increasing C in the free running circuit till I lowered F to the range of 10MHz.
I haven't seem a major deviation of the Xtal F, in the range of 5-10 KHz lower than the printed F on the Xtal. This could be due , as you point out to the C, or the cal on my DMM or the tolerance of the Xtals I pulled out of my junk box Some test Xtals are long ago pulls from radios, and I have no idea on the specs, only the marked Freq and that is down to only 2 decimal places. The only 'known' spec is the 16MHz one, 20pf load cap AT cut, which measured spot on.
Initially, I was assuming this circuit was close to the Pierce but I'm doubting that a little. Of course, may see different performance on a proper layout.

Hm. I wonder. Page 19 of the translated OPNA datasheet shows there's a selectable clock divider of 2,3, or 6 for the FM synth, but I'm not certain what else that changes. After all, the OPNA contains its own DAC, so there's no minimum clock speed to hold a serial bitstream. Anyway, when at a divider of 6 (claimed necessary for behavior above 4MHz), the output sample clock is Mclk/144. (Much like the OPL3's is Mclk/288, or the OPL2's is Mclk/72).

Beyonds changing the necessary tuning tables, this will also slightly affect ADSR rates, the timers, and the various free-running LFOs (e.g. "AMS" and "PMS"). Not certain exactly what they're using, since their rates don't seem to be tunable.

If we can extrapolate from the OPL3, the FM LFO is fixed at Sclk÷8192, and the AM LFO is fixed at Sclk÷13440. (MESS says these magic numbers are shared with the rest of the OPLx family, but who knows if that's true for the OPNx. Apparently the OPMx family can actually control the LFOs!)

I've only just started digging into the DS. But Is there a real need to maintain Sega's clk selection? With a 'new' design would there be an advantage to replicating Saga's HW? Would people want to use Saga VGM patches on a NES platform, sounds kind'of cool but IDK.
Yogi

yogi wrote:My observation with the original RC osc (no Xtal in circuit) measured @ ~16MHz.

There's no hysteresis with this driver, and no second-order effects. Even if RC there is 22µs, it's still going to self-bias right to the middle of the transfer function and ring as fast as it can.
I wonder if it's actually the parasitic inductance of the 10MΩ resistor that matters here? 10MΩ is so huge ... does the osc work if you omit it entirely?

I haven't seem a major deviation of the Xtal F, in the range of 5-10 KHz lower than the printed F on the Xtal. This could be due , as you point out to the C, or the cal on my DMM or the tolerance of the Xtals I pulled out of my junk box

You can usually get about 1000ppm of depression from nominal frequency by adjusting the load capacitance before the oscillator stops working... or about 16kHz on a 16MHz oscillator. Sounds consistent to me.

Initially, I was assuming this circuit was close to the Pierce but I'm doubting that a little.

It certainly should be... only differences that come to mind are:
1- they're omitting C2/using the 2Ck input as C2.
2- It's not a single inverter but instead an inverter and two NOR gates

Beyonds changing the necessary tuning tables, this will also slightly affect ADSR rates, the timers, and the various free-running LFOs (e.g. "AMS" and "PMS").
[…]
If we can extrapolate from the OPL3, the FM LFO is fixed at Sclk÷8192, and the AM LFO is fixed at Sclk÷13440.

I've only just started digging into the DS. But Is there a real need to maintain Sega's clk selection? With a 'new' design would there be an advantage to replicating Saga's HW? Would people want to use Sega VGM patches on a NES platform?

I don't think there's a need to maintain complete compatibility. It involves some things that can be compensated for (changing F numbers) and accepting the things that can't (5% increase of speed of ADSRs and LFOs). Is 5.8 Hz vs 6.1 Hz something a musician would care about? I'm definitely not the right person to ask.

OTOH, if we don't have another more convenient source of clock, using a 15.36÷2 driver vs an 8MHz source isn't so big.

One other question: does the YM2612 have the same input clock divider available as the YM2608? If so, would we want to consider running it off M2 instead? It should be equivalent to using a 5.4 MHz crystal. (and a corresponding slowing of the ADSRs and LFOs by 30%)

Last day and a half I've been testing the HCT74 osc. I've compiled a data set of the tests to try to understand the circuit better. Keep in mind that my test circuit is on solderless breadboard which has a lot of stray C and my DMM only has a range to 4MHz with 4 digit precision. In order to test in the ranges of interest, a prescaler was constructed using a second HCT74. The testing was done with a range of 3 R values, 4 C Values and 4 Xtal Frequencies. For each Xtal F, the output from the xtal osc was recorded as well as the free-running output for all RC combinations.
Two Xtals, the 11.525NHz and the 14.960MHz, were pulls with unknown specs, the other two, 16MHz and 18.432MHz, are AT cut 20pF load. The former two Xtals had unexpected performance with certain RC combos that leads me to suspect cut and load differences from the later Xtals.
Some of my conclusions:
1 I had a connection issue in the first build of the circuit that caused the strange behavior and the need for a inverter gate buffer. Through out this round of tests, the same R/C/Xtal combos that failed on the initial circuit now work.
2 The circuit is fairly forgiving with the RC selection but certain combos misbehave in a unexpected way. Example: The 16MHz Xtal running @ 19MHz with 5M/150pf but measured @ 16MHz with 5M/220pf. I'm sure some of these deviations are due to the mechanical problems with the breadboard as well as errors with my DMM coupling. But it could also indicate a cut/loading issue with the Xtal in some cases.
3 The Xtal to Free-running relationship seems to show a lower limit to acceptable RC Frequence. The Xtal Osc fails to lock when the free-running Freq is about 10% below the Xtal Freq. Further analysis is needed to understand the limits of Pat.'s description of the relationship between the RC TC and the Xtal Period.
At this point it should be clear that this circuit is quite capable, compact and could be considered as a replacement of a 'can' osc module if need be.
Yogi

Thanks for taking the time to explore this!

Naïve question: any idea why the free running frequencies not independent of the value of the missing crystal? The really visible outlier is no xtal/14.96MHz/10MΩ/220pF.

I've been trying to figure out a good way to graph this but there's four dimensions of input