MAD-1 discrete logic replacement

[Markfrizb]

I think magno mapped out that circuit. I don't see why it wouldnt work....

[getafixx]

Magno, have you got a working schematic then for that battery+sram design you mentioned?

[Markfrizb]

Here's a new direction.... Yoshi's island uses a small 8 pin chip for SRAM memory management with only 2 or 3 external components. The ones Nintendo used BA6129AF and the other is a MM1026AF.
I've sent an email to Maxim to see what the modern equivalent is. I'll keep you posted.

[lidnariq]

The "two resistors, two diodes" battery backup schematic is hard to beat for cheapness.

[Markfrizb]

Then why didn't Nintendo use this method?

[tepples]

I'm not sure if two resistors and two diodes are enough to prevent stray writes as the CPU begins to lose power. I seem to remember Super NES games being engineered not to require the player to hold reset while turning power off.

[infiniteneslives]

I'm not sure if two resistors and two diodes are enough to prevent stray writes as the CPU begins to lose power. I seem to remember Super NES games being engineered not to require the player to hold reset while turning power off.

Vcc has to be greater than Vbattery for SRAM's /CE to be enabled by the MAD-1, so maybe this is enough to prevent issues during power down.

The carts do prevent issues during power up by connecting CE to /RESET on most MAD boards from what I understand.

[magno]

Magno, have you got a working schematic then for that battery+sram design you mentioned?

Yes, I have. Here it is:

Yoshi's island uses a small 8 pin chip for SRAM memory management with only 2 or 3 external components. The ones Nintendo used BA6129AF and the other is a MM1026AF.

That component is outdated and you can't use it anyway: it controls SRAM's Vcc and /CS but paying attention only to Vcc. That means that, when Vcc drops below 3V, the chip MM1026AF detects the situation and triggers the low power mode: /CS = '1' and Vcc = 3.3V (it routes 3.3V from battery to SRAM Vcc). By doing it, you only can address 64K SRAM chips, since the address decoder would assert SRAM CS to activate/deactivate it. Besides this, there is another drawback: control logic is usually active low, so you will have to make "creative design" or use an inversor.

I'm not sure if two resistors and two diodes are enough to prevent stray writes as the CPU begins to lose power. I seem to remember Super NES games being engineered not to require the player to hold reset while turning power off.

I tell you: no, they are not enough. You must use a NPN transistor to properly assert SRAM /CS. However, diodes and resistors are enough to change between 5V and 3.3V while Vcc are dropping assuming /CS had been de-asserted by the NPN transistor prior to 5V fell below 3.3V.

[Markfrizb]

Which address decoder output is this per your Schematic? Is it tied to any of the outputs or a specific one?