Mode 20 vs. Mode 21 (aka LoROM vs. HiROM)

[MottZilla]

No. Nintendo had standards. And it's very clear that copiers did and still do exist. Developers couldn't just randomly map things where ever. Nintendo still made the cartridges.

[Near]

I've come up with a much better explanation of this after spending some time on it.

There are two primary ways ROMs can be mapped on the bus:

Mode 0:

Code: Select all

00-7f:8000-ffff -> 40-7f:0000-7fff
80-ff:8000-ffff -> c0-ff:0000-7fff

Mode 1:

Code: Select all

40-7f:0000-ffff -> 00-3f:8000-ffff
c0-ff:0000-ffff -> 80-bf:8000-ffff

The lefthand side reflects the native area, where ROM is mapped to linearly (each address is one byte further into the ROM.)
The righthand side is the "secondary" area.

Mode 0 never connects A15 to the ROM address lines. So the address is {A22-A16, A14-A0}
Mode 1 always connects A15 to the ROM address lines. So the address is {A21-A0}
By not connected, I mean the bits in the address are shifted right to compensate, so it's like A15 does not exist at all.

So in mode 0, the effect is that Bus 008000 = ROM 000000, Bus 018000 = ROM 080000, etc for the left-hand side. And Bus c00000 == Bus c08000 == Bus 008000, etc.

And in mode 1, the effect is that the left-hand side is linear: Bus c00000 = ROM 000000, Bus c08000 = ROM 008000. And the right-hand side has A15 always forced high because you can only access ROM in $xx:8000-ffff there. So Bus 008000 = ROM 008000, Bus 018000 = ROM 018000, etc.

Now of course, there are special case variations to this. Different PCBs will change where RAM is mirrored, some won't map anything into c0-ff:0000-7fff, some won't even map c0-ff at all (SuperFX), etc.

But we can narrow down LoROM vs HiROM to whether or not A15 is connected to the ROM pins. We don't need the complexity of "linear" and "shadow", or all that LoROM and HiROM entails. We simply need to provide where the ROM appears on the bus, and whether A15 is used or ignored. And that's enough to describe every commercial board ever released.

[kyuusaku]

byuu, you're such a programmer

I kind of consider what has been said incomplete and overcomplicated; technically LoROM can straightforwardly map up to 63.5 Mbits.

Heres my explanation:

LoROM / Mode 20: 00-FF:8000-FFFF (except for the two RAM banks where /ROMSEL isn't asserted), mirrored into 0000-7FFF on many banks (40-7F, C0-FF) where /ROMSEL is asserted because of partial decoding via A15.

HiROM / Mode 21: 00-FF:0000-FFFF (the entire address space, except for the 33 Mbits where /ROMSEL isn't asserted), this has a consequence of mapping ROM into banks (00-3F, 80-BF) where 0000-7FFF is not accessible so it must be accessed at a mirrored location where it is or significant ROM is forfeited.

The vectors in HiROM games must be placed at FFF? in ROM, LoROM needs them at 7FF? like a NES game.

All other mapping is achieved through secondary address decoding (partial and/or full) and scheme mixing.

[adam_smasher]

So semi-related n00b question: how does what cartridge you have in the cart slot remap/mirror the RAM that's inside the system?

[tepples]

It doesn't remap the RAM. Parts of the ROM that map to areas occupied by internal memory, such as banks $7E and $7F and the first half of banks $00-$3F and $80-$BF, are just made inaccessible by the address decoder.

[adam_smasher]

Hrm, I'm not sure I quite understand. Forgive me if I'm being thick, but Byuu sez:

Different PCBs will change where RAM is mirrored

Is that just a typo - did Byuu mean "Different PCBs will change where ROM is mirrored?"

But then he also says:

For one example, Ys 3 mirrors RAM to $70-7f:0000-ffff, but Fire Emblem Thracia 776 maps RAM to $70-7f:0000-7fff, and ROM to $70-7f:8000-ffff.

Or maybe he's talking about on-cart SRAM?

Or is the SNES wired somehow so that "failed" reads/writes to the cartridge slot can/do loop around to RAM or something?

It seems like the CPU should just be blindly "asking" the cart for a particular address - asserting (if that's the right term) certain lines on the cartridge slot and waiting for a response back from the cartridge slot on the next clock tick or whatever. How could those responses come from internal RAM, depending on the cart design? Rather, I would think that the SNES' wiring, before the cartridge even comes into play, should forward read/writes to the cart slot or to RAM based on the particular address requested.

[tepples]

But then he also says:

For one example, Ys 3 mirrors RAM to $70-7f:0000-ffff, but Fire Emblem Thracia 776 maps RAM to $70-7f:0000-7fff, and ROM to $70-7f:8000-ffff.

Or maybe he's talking about on-cart SRAM?

Yes, the same sort of RAM that's traditionally mapped to $6000-$7FFF on an NES. As I understand it, mode 21 games map this to $306000-$307FFF, $316000-317FFF, ..., $3F6000-$3F7FFF.

Rather, I would think that the SNES' wiring, before the cartridge even comes into play, should forward read/writes to the cart slot or to RAM based on the particular address requested.

I think that's what the /CART signal between A23 and D4 is for: an enable for the PRG ROM.