MMC2. Purpose of Connections?

[MottZilla]

I was looking at a pinout of the MMC2 on kevtris's page. It seems that a large number of CHR Address lines are present. But I couldn't really think of why some are. I can understand the upper address lines as they are important for determining if tile FD or FE is being read. But why are CHR A0, 1, 2, and 3 connected?

Another point I was thinking about is when tile FD or FE is fetched there are two reads that occur for reading both bit planes of the tile. But any read to the $xFDx or $xFEx areas is supposed to set or clear the latches. So how is it implemented to make sure that the switch occurs after the second read is complete? Does the hardware implement a small cycle timer or just a single delay flag or what?

I thought that if you ignore reads from $xFD0 to $xFD7 and only watch when there is a read with A3 set ($xFD8 to $xFDF) and set or clear the latch after the read is complete then you don't need any sort of timer, maybe just a delay type of flag.

[Dwedit]

Maybe they just simply didn't make it as efficient as they could have. With the MMC1, Nintendo aggressively reduced pin count, but maybe they didn't care as much for MMC2, since it was used in a total of one game. Does MMC4 have any redundant pins?

[Grapeshot]

A3 is used to make sure the latch isn't switched until the second byte of tile $FD or $FE is read, and if this isn't emulated on MMC4, Fire Emblem has garbage on the right side of text boxes.

A0, A1, and A2 are less clear. I think according to the MMC2 patent, for one of the pattern tables the MMC2 was only supposed to switch banks on the first line of a tile, but that wasn't implemented in the final chip.

[MottZilla]

Well that's interesting. Maybe the unused $8000 and $9000 registers had to do with that cut/unimplemented behavior. So really A0, A1, A2 probably serve no purpose.

About the second read, does that mean if you read from $xFD0 to $xFD7 it won't toggle the latch? Will only reading that has A3 set cause the latches to toggle?

And I'm not sure if anyone even has a MMC4 pinout.

[infiniteneslives]

And I'm not sure if anyone even has a MMC4 pinout.

The PCB always has most of it! Although I guess he doesn't count as someone...

Sat down with famicom wars and the multimeter this evening. Only took us ~24 years, but it looks like we've now got pinouts of all MMC's documented:

Code: Select all

1 ? (floating)
2 PRG /CE (n)
3 CHR /RD (n)
4 CHR A3 
5  ? (floating)
6 GND
7 CHR A4
8 CHR A5
9 CHR A6
10 CHR A7
11 ? (floating)

12 CHR A8
13 CHR A9
14 CHR A10
15 CHR A11
16 CHR A12
17 CHR A13
18 GND
19 CHR ROM A12
20 CHR ROM A13
21 CHR ROM A14
22 CHR ROM A15

23 WRAM /CE
24 tied to pin 23 (WRAM /CE)
25 WRAM CE
26 CIRAM A10
27 Vcc
28 GND
29 M2
30 PRG A14 (n)
31 PRG A13 (s)
32 PRG A12 (s)
33 tied to pin 32 (PRG A12)

34 PRG ROM A14
35 PRG ROM A15
36 PRG ROM A16
37 PRG ROM A17
38 PRG ROM /CE 
39 PRG D4
40 PRG D3
41 PRG D2
42 PRG D1
43 PRG D0
44 PRG R/W (NES & WRAM)

Sorry my notes don't exactly follow the naming convention. I'm working on it...

Looks basically like the MMC2 except they cut out the (unused ?) CHR A0-A2. And added on WRAM control and 512KB PRG ROM. Interesting how a few of the pins were shorted together on the PCB, but MMC3 has some as well I guess.