14 months later, the chip was finally delayered; polysilicon was traced in about 5 days, diffusion after another 4 days, and buried contacts 1 day later.
After about a day spent processing the layer images, fixing mistakes, and various tweaking, I present to you:
The Visual 2C02
The simulator currently has an old test program I wrote for it (which performs a sprite DMA and then tries to enable rendering), but it doesn't really accomplish much because the PPU takes at least a complete frame to come out of reset and actually start accepting writes to various registers (as observed and documented here).
Names have been assigned to a preliminary set of nodes and buses:
- all of the external pins (and their corresponding internal signals)
- the pixel counter (hpos*)
- the scanline counter (vpos*)
- the SPR-RAM address (spr_ptr*)
- the I/O register signals (w2000, w2001, w2003, w2004, w2005a, w2005b, w2006a, w2006b, w2007, r2002, r2004, r2007)
- the VRAM address register (vramaddr_t* and vramaddr_v*) plus fine X scroll (finex*)
- the writable bits of $2000 (addr_inc, spr_pat, bkg_pat, spr_size, slave_mode, enable_nmi)
- the writable bits of $2001 (pal_mono, bkg_clip, spr_clip, bkg_enable, spr_enable, emph*)
- the readable bits of $2002 (spr0_hit, spr_overflow, vbl_flag)
- the $2007 read buffer (inbuf*)