VRC2a as VRC2b posible?

[jpx72]

Is it possible to use VRC2a as VRC2b?

From the wiki page
- VRC2a has A0 and A1 "backwards" from the norm.
okay, but also
- Additionally, VRC2a has 7-bit wide CHR registers, whereas VRC2b has 8-bit wide CHR registers.
here I am lost...so what other change must be done? Thanks!

[Bregalad]

The chip is the same, the only difference is the traces on the PCB.

[lidnariq]

What Bregalad said, or specifically:

If you look at the pinout for how the VRC2 is wired in the VRC2b variant, the difference to VRC2a is:
pins 3 and 4 are swapped
pin 21 is n/c
pins 22-28 are wired such that the pin labelled chr a11 goes to chr a10, a12 to a11, &c.

[jpx72]

Thanks for the answer, so just to be sure if I got the changes right:

Code: Select all

              VRC2b variant                              VRC2a variant
                  .--\/--.                                   .--\/--. 
   (n) CPU A13 -> |01  40| -- +5V             (n) CPU A13 -> |01  40| -- +5V
   (n) CPU A14 -> |02  39| -> PRG A17 (r)     (n) CPU A14 -> |02  39| -> PRG A17 (r)
    (s) CPU A1 -> |03  38| -> PRG A15 (r)    * (s) CPU A0 -> |03  38| -> PRG A15 (r)
    (s) CPU A0 -> |04  37| <- CPU A12 (s)    * (s) CPU A1 -> |04  37| <- CPU A12 (s)
   (n) PPU A12 -> |05  36| -> PRG A14 (r)     (n) PPU A12 -> |05  36| -> PRG A14 (r)
   (n) PPU A11 -> |06  35| -> PRG A13 (r)     (n) PPU A11 -> |06  35| -> PRG A13 (r)
   (n) PPU A10 -> |07  34| -> PRG A16 (r)     (n) PPU A10 -> |07  34| -> PRG A16 (r)
   (r) PRG /CE <- |08  33| <- CPU D0 (s)      (r) PRG /CE <- |08  33| <- CPU D0 (s)
   (n) CPU R/W -> |09  32| <- CPU D1 (s)      (n) CPU R/W -> |09  32| <- CPU D1 (s)
   (r) CHR /CE <- |10  31| <- CPU D2 (s)      (r) CHR /CE <- |10  31| <- CPU D2 (s)
   (n) PPU A13 -> |11  30| <- CPU D4 (s)      (n) PPU A13 -> |11  30| <- CPU D4 (s)
   (n) PPU /OE -> |12  29| <- CPU D3 (s)      (n) PPU /OE -> |12  29| <- CPU D3 (s)
   (n) PPU A10 -> |13  28| -> CHR A17 (r)     (n) PPU A10 -> |13  28| -> CHR A16 (r) *
   (n) /ROMSEL -> |14  27| -> CHR A15 (r)     (n) /ROMSEL -> |14  27| -> CHR A14 (r) *
        (n) M2 -> |15  26| -> CHR A12 (r)          (n) M2 -> |15  26| -> CHR A11 (r) *
             ? -- |16  25| -> CHR A14 (r)               ? -- |16  25| -> CHR A13 (r) *
 VRC4 (n) /IRQ <- |17  24| -> CHR A13 (r)   VRC4 (n) /IRQ <- |17  24| -> CHR A12 (r) *
             ? -- |18  23| -> CHR A11 (r)               ? -- |18  23| -> CHR A10 (r) *
 VRC4 WRAM /CE <- |19  22| -> CHR A16 (r)   VRC4 WRAM /CE <- |19  22| -> CHR A15 (r) *
           GND -- |20  21| -> CHR A10 (r)             GND -- |20  21| -> NC *
                  `------'                                   `------'

* - difference

[lidnariq]

I believe that is correct.